In the fabrication of semiconductor components, the various devices are formed in layers upon an underlying substrate that is typically composed of silicon, germanium, or gallium arsenide. The various discrete devices are interconnected by metal conductor lines to form the desired integrated circuits. The metal conductor lines are further insulated from the next interconnection level by thin films of insulating material deposited by, for example, CVD (Chemical Vapor Deposition) of oxide or application of SOG (Spin On Glass) layers followed by fellow processes. Holes, or vias, formed through the insulating layers provide electrical connectivity between successive conductive interconnection layers. In such microcircuit wiring processes, it is desirable that the insulating layers have a smooth surface topography, since it is difficult to lithographically image and pattern layers applied to rough surfaces.
Conventional chemical/mechanical polishing (CMP) has been developed for providing smooth semiconductor topographies. Chemical/mechanical polishing (CMP) can be used for planarizing: (a) insulator surfaces, such as silicon oxide or silicon nitride, deposited by chemical vapor deposition; (b) insulating layers, such as glasses deposited by spin-on and reflow deposition means, over semiconductor devices; or (c) metallic conductor interconnection wiring layers. Semiconductor wafers may also be planarized to: control layer thickness, sharpen the edge of via "plugs", remove a hardmask, remove other material layers, etc. Significantly, a given semiconductor wafer may be planarized several times, such as upon completion of each metal layer. For example, following via formation in a dielectric material layer, a metallization layer is blanket deposited and then CMP is used to produce planar metal studs.
Briefly, the CMP process involves holding and rotating a thin, reasonably flat, semiconductor wafer against a rotating polishing surface. The polishing surface is wetted by a chemical slurry, under controlled chemical, pressure, and temperature conditions. The chemical slurry contains a polishing agent, such as alumina or silica, which is used as the abrasive material. Additionally, the slurry contains selected chemicals which etch or oxidize selected surfaces of the wafer during processing. The combination of mechanical and chemical removal of material during polishing results in superior planarization of the polished surface. In this process it is important to remove a sufficient amount of material to provide a smooth surface, without removing an excessive amount of underlying materials. Accurate material removal is particularly important in today's submicron technologies where the layers between device and metal levels are constantly getting thinner.
One problem area associated with chemical/mechanical polishing is in the step of removing the planarized wafer from the polishing surface without damaging the wafer. In addition to its function as a chemical and mechanical abrasive, the chemical slurry acts as a lubricant similar to oil. As the process proceeds, all gases, e.g., air, are expelled from between the wafer and the polishing pad. The resultant effect is the formation by adsorption of a thin film between the surface of the polishing pad and the surface of the wafer. The film of slurry adheres to the surfaces of both the semiconductor wafer and the polishing pad. Thus, when the CMP process is complete and the wafer is to be removed for the next processing step, the semiconductor wafer clings to the polishing pad. It is necessary to break the seal between the wafer and the polishing pad without damaging the wafer and to transport the wafer to the cleaning station. One method that has been used to accomplish this task is to lift the wafer in the carrier head vertically from the polishing pad. However, the force that adheres the wafer to the polishing pad can be sufficient to pull the wafer from the carrier head, thus complicating retrieval of the wafer or damaging the wafer. An alternative method employed is that of sliding the wafer off the edge of the polishing pad, thereby breaking the seal. However, this often results in the wafer falling off the edge of the polishing pad and being damaged as it strikes some part of the processing chamber.
Additionally, the endpoint of the CMP process may have to be determined experimentally, i.e., the wafer lifted from the polishing surface and visually or optically inspected after a specific processing time. This introduces a significant opportunity for wafer damage, as the inspection may have to be performed several times until the desired finish or surface removal has been accomplished.
Accordingly, what is needed in the art is a polishing apparatus and method for its use that will efficiently break the seal between a semiconductor wafer and a CMP polishing pad without damage to the semiconductor wafer.